Surrounding Gate Transistors – Price + Size + Performance
Intel co-founder Gordon Moore predicted in 1965 that the number of transistors per silicon chip would double every two years. This came to be known as Moore´s Law which has been proven accurate for the last fifty years. Many scientists argue that the law is soon to be broken because of physical limitations. The end of Moore´s law would mean a stagnation in computer processing and power and could cause economic issues because changing the whole computer industry to adapt to a new technology would generate really high costs.
Unisantis electronics in association with the Belgian research institute Imec have proposed a solution that not only allows the size to get smaller, but also will have minimum effect in manufacturing process. The Surrounding Gate Transistor (SGT) has a vertical design (as opposed to commonly used transistors which have a horizontal design), this means 50% less occupied area while electron mobility could increase by 300%. Additionally, the vertical structure improves operating voltage, stability, and leakage current.
Nowadays, transistors used are about 10 nm, but smaller sizes come with problems such as quantum tunneling which allows the electrons to flow from one gate to the next. SGT´s surround the channel on all sides and that provides better control over the channel. The surrounding gate topology enables a single SRAM cell using just six 5 nm transistors.
Also, Unisantis has developed the process for STG production using the technology available nowadays. As a result, the implementation of this technology in the sector will not mean a huge impact on costs.
Other solutions have been proposed such as software improvements, and parallelization, but these are not long-term solutions since a physical barrier is soon to be reached. Other solutions are too expensive to implement, or the idea is still in early steps. Many industries are working toward solving this problem, but few viable solutions have been reached.
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