The ESP32-C3 is a WiFi SoC that contains a RISC-V core in place of the Tensilica core in the ESP32 we are all familiar with. It uses the ESP8266 pin-out. As with other ESP32 family members, this one delivers b/g/n WiFi and Bluetooth LE 5, where it differs is the RISC-V 32 Single-core processor with a clock speed of up to 160 MHz. There is 400 KB of SRAM and 384 kB ROM storage space built-in. It is confirmed that ESP32-C3 WiSoC is pin to pin compatible with ESP8266. It works with the ESP32 development framework too. It consumes only 5uA in deep sleep mode. Pricing is also going to be similar to ESP8266.
As RISC-V is catching up with ARM and other mainstream CPU cores, this move from Espressif was largely anticipated. RISC-V being an open standard instruction set architecture, developers will have better control over the registers of the microcontroller and can write firmware which is way more efficient in terms of memory usage and power consumption. Currently, ESP32 and ESP8266 use Tensillica’s Xtensa 32 bit dual or single-core CPU with Xtensa LX6 instruction set architecture.
The arrival of this new SoC is going to give head-on competition to the cheap wireless SoCs such as the Bouffalo Lab’s BL602. So an upgrade path to a more proficient part with minimal new hardware design requirements could be a powerful motivation for large customers to stay with Espressif.
It’s also to be expected that a standard RISC-V toolchain could also be used instead of the device-specific ones for current Espressif offerings. It is not expected to be open-source replacements for the blobs that drive the on-board peripherals, as the new chip will share the same closed-source IP as its predecessors for them. Perhaps if the PINE64 initiative to reverse engineer blobs for the BL602 will make something fruitful, a similar effort is desired here by the community.
Read more: ESPRESSIF LEAKS RISC-V POWERED ESP8266 PIN-COMPATIBLE ESP32-C3
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