Range of I2C-bus NXP extends with no-offset buffer

The PCA9525 is a monolithic CMOS integrated circuit for bus buffering in applications including I²C-bus, SMBus, DDC, PMBus, and other systems based on similar principles.

The buffer extends the bus load limit by buffering both the SCL and SDA lines, allowing the maximum permissible bus capacitance on both sides of the buffer.

The PCA9525 includes a unidirectional buffer for the clock signal, and a bidirectional buffer for the data signal. Slave devices which employ clock stretching are therefore not supported.

In its most basic implementation, the buffer will allow an extended number of slave devices to be attached to one (or more) master devices. In this case, all master devices would be positioned on the Sxx_IN side of the PCA9525.

The direction pin (DIR) further enhances this function by allowing the unidirectional clock signal to be reversed, thus allowing master devices on both sides of the buffer.


Features and benefits

  • Simple impedance isolating buffer for 2-wire buses
  • 4 mA maximum static open-drain pull-down capability supports a wide range of bus standards
  • Works with I²C-bus (Standard-mode, Fast-mode), SMBus (standard and high power mode), and PMBus
  • Fast switching times allow operation in excess of 1 MHz
  • Enable allows bus segments to be disconnected
  • Hysteresis on inputs provides noise immunity
  • Operating voltages from 2.7 V to 5.5 V
  • Very low supply current
  • Uncomplicated characteristics suitable for quick implementation in most common 2-wire bus applications


  • Electronic signs and displays
  • Game consoles/boxes
  • Gaming machine networks
  • TV/projector/monitor interconnection (DDC)
  • Power management systems
  • Desktop and portable computers
  • Security systems

Range of I2C-bus NXP extends  with no-offset buffer

NXP Semiconductors has introduced its first no-offset I2C-bus buffers, which are designed to isolate capacitance and so allow interface with other bus buffers.

Significantly, the bus buffers use the no-offset scoreboard method to decide signal direction, rather than using a directional pin and relying on offset voltages to control direction and prevent bus latch-up.

As a result the PCA9525 and PCA9605 no-offset buffers are interoperable even with static offset or incremental bus buffers, allowing easy design-in regardless of which other devices are on the bus, said the supplier.

While I2C buses have traditionally been used in computing, consumer and portable applications where only short bus lengths are needed.

NXP claims it offers a way around this limitation by allowing buses to be broken into segments or branches to isolate the bus capacitance into lower capacitive segments meeting I2C-bus specifications.

The capacitance isolating buffer for 2-wire I2C or SMBus buses, allows buses to be broken into segments or branches to isolate the bus capacitance into lower capacitive segments with the PCA9605 supporting the higher capacitance limits of Fm+

As a result “I2C-based monitoring and control systems which can serve with hundreds of nodes and/or bus wiring lengths up to 1 km (0.62 miles) at lower frequencies,” claimed NXP.


For more read: Range of I2C-bus NXP extends  with no-offset buffer

About The Author

Ibrar Ayyub

I am an experienced technical writer holding a Master's degree in computer science from BZU Multan, Pakistan University. With a background spanning various industries, particularly in home automation and engineering, I have honed my skills in crafting clear and concise content. Proficient in leveraging infographics and diagrams, I strive to simplify complex concepts for readers. My strength lies in thorough research and presenting information in a structured and logical format.

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