Monolithic terabyte memory IC

Crossbar, the RRAM specialist, says it has solved a major obstacle to RRAM’s commercialisation – what Crossbar calls ‘sneak path current’ which is akin to leakage in CMOS circuits but particularly destructive in RRAMS.

This, breakthrough, says a Crossbar press release: “Signals Crossbar’s 3D RRAM readiness for commercialisation of Terabyte storage-on-a-chip.”

So how far away from production is an 8Tbit memory chip?

A long way it seems. It would need a 20nm process to make a 1Tb chip, I am told by Crossbar vp Subain Dubois. The densest chip Crossbar has made so far is 1Mbit. The densest NAND is 128Gbit.

The most advanced process Crossbar has used for its memory IP block is 40nm.

If a 1Tb chip needs 20nm, what would an 8Tb chip need?

Crossbar is not saying. It has prototyped its cell at 8nm but is not saying how much silicon area it occupies.

The only metric on cell size which Crossbar will give is 4S² – where S is the smallest feature possible on the process. Since it’s not usually revealed what the smallest dimension obtainable on any process is these days, it seems the size of the Crossbar cell at any given node will remain unknown – unless Crossbar chooses to reveal it. Which it doesn’t.

Assuming that a 14nm process could deliver a 4Tb chip then it is possible to envisage an 8nm process delivering an 8TB chip.

But Crossbar does not claim that. However it can build its memory cell upwards – in a 3D structure – and so by adding layers it can add to the density of its devices. But Crossbar is not saying how many levels it needs to be able to deliver any particular density.

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