ARM has added to its CoreLink Cache Coherent Network (CCN) SoC interconnects, which deliver a flexible architecture from sensors to servers.
The CoreLink CCN-502 and CoreLink CCN-512 interconnects extend the current family for data center and infrastructure equipment that scales from the edge of the network to the core.
The entire family of CoreLink CCN interconnects offer enterprise-class features such as RAS, ECC and advanced QoS to address a wide range of infrastructure SoCs ranging from 1 to 48-cores of CPU that can be coupled with a variety of heterogeneous compute elements.
All CoreLink CCN interconnects include native ARM AMBA 5 CHI interfaces providing high frequency, non-blocking data transfers and an integrated Level 3 Cache and Snoop Filter.
CoreLink CCN-502 is an area-optimized interconnect for up to four quad-core processor clusters, offering the most cost and power-efficient solution in the CoreLink CCN family. Applications may include small cell base stations and sub-10W Power-over-Ethernet wireless access points.
Key benefits and features of the CoreLink CCN-502 include:
· 70% area reduction over CoreLink CCN-504 at 1MB
· Optional, integrated Level 3 System Cache configurable up to 8MB
· High frequency, high performance interconnect supporting up to 0.8Tb/s sustained bandwidth
· 1 to 4 processor clusters including ARM Cortex®-A53 and Cortex-A57 processors with AMBA 5 CHI
· 1 to 4 channels of DDR3/4 memory with DMC-520 supporting 72-bit ECC DIMMs
· Up to 9 1/O coherent ports with AMBA 4 AX14/ACE-Lite interfaces in addition to CPU and DMC ports
The CoreLink CCN-512 is the highest performance solution in the CoreLink CCN family and offers partners the ability to create dense, 48-core heterogeneous compute solutions with mix of CPUs, DSPs and accelerators and bandwidths up to 1.8 terabits per second.
For more detail: ARM adds to CoreLink SoC interconnects