TI adds phase detector and PLL to precision



The LMX2581 is an ultra low noise wideband frequency synthesizer which integrates a delta-sigma fractional N PLL, a VCO with fully integrated tank circuit, and an optional frequency divider.

The LMX2581 integrates several low-noise, high precision LDOs to provide superior supply noise immunity and more consistent performance. When combined with a high quality reference oscillator, the LMX2581 generates a very stable, ultra low noise signal. The internal VCO can be bypassed so that an external VCO can be used.



General Features

    • 50 – 3760 MHz Operating Frequency
    • Low Voltage Logic Compatibility
    • Digital Lock Detect
    • 32 Pin QFN Package

High Performance PLL

    • –229 dBc/Hz Normalized PLL Phase Noise
    • –120.8 dBc/Hz Normalized PLL 1/f Noise
    • 200 MHz Maximum Phase Detector Frequency
    • Programmable Charge Pump Current

Broadband Multi-Core VCO

    • Tuning Range: 1880 – 3760 MHz
    • –137 dBc/Hz Phase Noise @ 1 MHz for a 2.5 GHz Carrier
    • Programmable Output Power
    • Programmable Option to Use an External VCO

Low Noise VCO Divider

  • Programmable to divide by 1 (bypass), 2, 4, 6, 8, … , 38
  • –155 dBc/Hz Noise Floor

TI adds phase detector and PLL to precision RF synthesiser

Texas Instruments has introduced a wideband frequency synthesiser with integrated low phase-noise voltage-controlled oscillator.

The device combines a low noise phase-locked loop (PLL) and a phase detector in a  frequency synthesiser that outputs 50 to 3760 MHz.

Designated the LMX2581, the chip’s phase detector frequency of 200MHz and PLL normalised phase noise of -229dBc/Hz provides a precision local oscillator for RF front ends.

The integrated VCOs allow the device to output frequencies from 50MHz to 3760MHz, eliminating the multiple VCO/PLL combinations typically required to support a broad range of applications.

There is also the option to bypass its internal multi-core VCO in favour of an external VCO.

The frequency synthesiser integrates a delta-sigma fractional-N PLL; a multi-core VCO with tank circuit; optional frequency divider; two differential RF output buffers that can deliver 10 dBm single-ended on each side; and several low-noise, high precision low dropout regulators (LDOs).


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