PULPino is a competitive, open-source 32-bit RISC-V microcontroller developed by ETH Zurich and the University of Bologna. Based on the RI5CY core, it features advanced peripherals like I2S, I2C, SPI, and UART, alongside robust low-power capabilities suitable for embedded OSs like FreeRTOS. The design is mature, having been taped out in 65nm ASIC, and offers full debug support via GDB and KCacheGrind for both FPGA and RTL simulation without registration requirements.
Parts used in the PULPino:
- RI5CY 32-bit RISC-V core
- I2S peripheral
- I2C peripheral
- SPI peripheral
- UART peripheral
- JTAG interface
- Boot ROM
- External SPI flash
- Event unit
What you will get is a competitive, state-of-the-art 32-bit processor based on the RISC-V architecture, with a rich set of peripherals, and full debug support. At ETH Zurich and Università di Bologna we have put many of the ideas that we have developed through our research on ultra-low-power parallel processing (PULP project) into PULPino. It is the little hip brother to its more serious bigger brothers.
State-of-the-Art Microcontroller Core
PULPino is based on RI5CY, an optimized 32-bit RISC-V core developed at ETH Zurich and Universita’ di Bologna. The core has an IPC close to 1, full support for the base integer instruction set (RV32I), compressed instructions (RV32C) and partial support for the multiplication instruction set extension (RV32M). It implements several ISA extensions such as: hardware loops, post-incrementing load and store instructions, ALU and MAC operations, which increase the efficiency of the core in signal processing applications.
A Rich Set of I/O Peripherals
For communication with the outside world, PULPino contains a broad set of peripherals, including I2S, I2C, SPI and UART. The platform internal devices can be accessed from outside via JTAG and SPI, which allows pre-loading RAMs with executable code. In standalone mode, the platform boots from an internal boot ROM and loads its program from an external SPI flash.
Low-Power, but Powerful
To allow embedded operating systems such as FreeRTOS to run, a subset of the privileged specification is supported. Moreover, PULPino comes with many of the low-power features we developed in the PULP Project: when the core is idle, the platform can be put into a low power mode, where only a simple event unit is active and everything else is clock-gated and consumes minimal power (leakage). A specialized event unit wakes up the core in case an event/interrupt arrives.
Not a Toy Design
PULPino is a mature design: it has been taped-out as an ASIC in UMC 65nm in January 2016. The PULPino platform is available for RTL simulation as well for FPGA mapping. It has full debug support on all targets. In addition we support extended profiling with source code annotated execution times through KCacheGrind in RTL simulations and debug via GDB.
And it is free, no registration, no strings attached, you can use it, change it, adapt it, add it to your own chip, use it for classes, research, projects, products… We just ask you to acknowledge the source, and if possible, let us know what you like and what you don’t like.
For more detail: We are happy to share our FREE and OPEN-SOURCE microprocessor system PULPino!
- What architecture does PULPino use?
PULPino uses a 32-bit RISC-V architecture based on the RI5CY core. - Can PULPino run embedded operating systems?
Yes, a subset of the privileged specification is supported to allow OSs like FreeRTOS to run. - How does PULPino achieve low power consumption?
The platform enters a low power mode where everything is clock-gated except a simple event unit that wakes the core upon an interrupt. - Is PULPino available for hardware implementation?
Yes, the platform is available for FPGA mapping and was taped out as an ASIC in UMC 65nm. - Does PULPino require registration to use?
No, the microprocessor system is free, open-source, and requires no registration or strings attached. - What debug tools are supported for PULPino?
It supports full debug via GDB and extended profiling with source code annotated execution times through KCacheGrind. - How can the platform boot in standalone mode?
In standalone mode, the platform boots from an internal boot ROM and loads its program from an external SPI flash. - Which instruction set extensions are implemented?
It implements hardware loops, post-incrementing load/store instructions, ALU operations, and partial support for multiplication (RV32M).
