EnSilica adds DSP to RISC cores
EnSilica has added a 64-bit precision, fully-pipelined MAC unit to its RISC core to deliver the eSi-3260 for audio, sensor hub, motion control and touch screen applications.
In addition to 32-bit data, the MAC unit supports dual 16-bit SIMD (single instruction multiple data) multiply and MAC operations. Uniquely, full complex multiplication is also supported, performing four multiplies and two additions per cycle.
The inclusion of saturating and rounding arithmetic, along with instructions to support bit-reversed addressing, provides FFT acceleration and accuracy.The eSi-3260 employs a 5-stage pipeline which has been optimized to deliver market-leading performance in mainstream process nodes with frequencies of over 1GHz obtainable in a 28nm process with dynamic power of 14μW/MHz.
This can be reduced to 3μW/MHz when optimizing the processor for power, rather than frequency. A flexible memory architecture, with either native, AXI or AHB interfaces, allows the inclusion of instruction and data caches as well as tightly coupled memories for running code that is timing critical. The addition of a cache facilitates high-performance operations even when they are run from embedded Flash.
The radix-8 fast divide and square root options enable 32-bit integer division and square root operations to be reduced to six cycles, greatly decreasing the cycle count in sensing operations where these operations are key to the code operation.
An optional, fully pipelined single precision floating point capability helps accelerate high dynamic range calculations for applications such as gesture recognition and fingerprint detection. Custom instruction support allows a further level of application acceleration such as IIR and logarithmic DSP operations or cryptographic operations for standards including ECC, RSA, AES and SHA.
For more detail: EnSilica adds DSP to RISC cores
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