Summary of UK start-up makes 28nm FD-SOI embedded memory “breakthrough”
SureCore successfully taped out a low-power SRAM IP demonstrator chip using STMicroelectronics' 28nm FD-SOI process. This device validates a patented array control scheme, achieving over 50% power savings compared to current offerings. The design utilizes advanced statistical models and detailed analysis, showing significant reductions in read/write power and leakage. While built on FD-SOI, the technology is process-agnostic and compatible with bulk CMOS and FinFET nodes.
Parts used in the SureCore SRAM Demonstrator:
- Low power SRAM IP demonstrator chip
- STMicroelectronics 28nm Fully Depleted Silicon-on-Insulator (FD-SOI) process
- Patented array control scheme
- Patented sensing scheme
- Advanced statistical models
- Detailed analysis tools
SureCore, the UK-based embedded memory process developer, has announced that it has taped out its low power SRAM IP demonstrator chip in STMicroelectronics’ 28nm Fully Depleted Silicon-on-Insulator (FD-SOI) process.
The device will be used to validate the benefits of the start-up’s patented array control and sensing scheme, which is claimed to lowers active power consumption to deliver greater than 50% power savings compared to current offerings in the same process.
The SRAM IP memory was designed through a combination of detailed analysis and the use of advanced statistical models.
“In post layout simulations the memory showed 75% less power for read cycles and 50% for write cycles. In addition, the technology promises improved leakage performance saving between 20% and 40% depending on operating corner,” said the company.
– See more at: http://www.electronicsweekly.com/news/components/memory/uk-start-up-makes-28nm-fd-soi-embedded-memory-breakthrough-2013-10/#sthash.4M5i0fPB.dpuf
This is a major milestone for the company – the demonstrator device will allow us to take the next steps commercially,” said Paul Wells, sureCore CEO.
Although it is implemented in an FD-SOI process, Wells says the technology is not process specific and will map to both bulk CMOS and FinFET technologies.
“We are currently working closely with partners to implement this in 40nm and 28nm bulk CMOS,” said Wells.
– See more at: http://www.electronicsweekly.com/news/components/memory/uk-start-up-makes-28nm-fd-soi-embedded-memory-breakthrough-2013-10/#sthash.4M5i0fPB.dpuf
- What process was used for the demonstrator chip?
The chip was taped out in STMicroelectronics' 28nm Fully Depleted Silicon-on-Insulator (FD-SOI) process. - How much power savings does the new SRAM offer?
The technology delivers greater than 50% power savings compared to current offerings in the same process. - Does the technology work only on FD-SOI processes?
No, the technology is not process specific and will map to both bulk CMOS and FinFET technologies. - What were the results of post layout simulations?
Simulations showed 75% less power for read cycles and 50% less power for write cycles. - How does the technology affect leakage performance?
The technology promises improved leakage performance saving between 20% and 40% depending on operating corner. - Which other process nodes is SureCore working to implement this technology in?
The company is working closely with partners to implement this in 40nm and 28nm bulk CMOS. - How was the SRAM IP memory designed?
The memory was designed through a combination of detailed analysis and the use of advanced statistical models. - Who is the CEO of SureCore?
Paul Wells is the CEO of SureCore.
