This is an easy-to-build project and it is the most cost-effective and high-performance frequency multiplier, which instigates analog phase lock loop techniques. The circuit provides high-quality, high-frequency output from lower frequency crystal or clock input. The project can be used as a crystal frequency oscillatorclock multiplier and frequency translation. Using phase-locked-loop (PLL) techniques, the device uses a standard fundamental mode, inexpensive crystal to produce an output clock up to 200Mhz.  On-board jumpers are provided to select from nine different multiplication factors, which output many common frequencies.  The device also has an output enable pin that tri-states the clock output when the enable pin is taken low. The chip is intended for clock generation and frequency translation with low output jitter.

Refer to the table below for jumper settings to change the frequency multiplexing.

  • Connections for Clock Input: CN1 Clock input 1- 50Mhz, Use J2, and J3 for frequency output settings.
  • For Internal Clock Generator: Use crystal Y1, Capacitor C1, and C2

A parallel resonant, fundamental mode crystal should be used. The device crystal connections and capacitor connections are provided. These capacitors are used to adjust the stray capacitance of the board to match the nominally required crystal load capacitance. Because load capacitance can be only be increased in this trimming process. Crystal Capacitors, if needed, must be connected from each of the pins X1 and X2 to the ground.

The value (in pF) of these crystal capacitors should equal C-L x 2 in this equation, C-L=crystal capacitance in pF. Example: For a crystal with a 15pF load capacitance, each crystal capacitor would be 30pF.   


  • Power Supply 5V DC (Range 3 to 5 V DC)
  • Zero ppm multiplication error
  • Output Load 12mA Max
  • Input crystal frequency of 5Mhz to 30Mhz
  • Output Duty Cycle 50%
  • Input Clock Frequency of 1-50Mhz
  • Output Clock Frequencies up to 200Mhz
  • 9 Selectable Frequencies Controlled by Jumper
  • Peak to Peak Jitter Less than 200ps over 200ns Interval (100-200Mhz)
  • Low Period Jitter 20ps (100-200Mhz)
  • Tri-States Output for Board Level Testing
  • PCB dimensions: 25.72 x 17.94 mm


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Muhammad Bilal

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