In digital electronics, fan-out is defined as the number of gate inputs that the output of a single logic gate can feed. It is very important in digital systems for a single logic gate to drive other gates or devices. In this case, a buffer can be used between the logic gate and the devices it will drive. Clock buffer is also called as fan-out buffer. The IDT clock buffer clock divider and clock multiplexer portfolio includes devices with up to 27 outputs. Differential outputs such as LVPECL, LVDS, HCSL, CML, HSTL, as well as selectable outputs, are supported for output frequencies up to 3.2 GHz and single-ended LVCMOS outputs for frequencies up to 350MHz.
Modern digital systems often require many high quality clocks at logic levels that are different from the logic level of the clock source. Extra buffering may be required to guarantee accurate distribution to other circuit components without loss of integrity. Many systems require low jitter multiple system clocks for mixed signal processing and timing. The circuit shown in interfaces the ADF4351 integrated phase-locked loop (PLL) and voltage-controlled oscillator (VCO) to the ADCLK948, which provides up to eight low voltage differential signaling (LVDS) outputs from one differential output of the IDT 8SLVD1208-33.
For more detail: Increasing Outputs from a Clock Source
