Gen 3.2 PCS Board Design




Gen 3.2

Gen 3.1

Microcontroller-related

Other Microserver-Related

 

Introduction

The purpose of this page is to document the Vexcel microserver Power Conditioning Subsystem (PCS).

Gen 3.2 PCS Board Design Schemetic

Reference figures

This diagram shows the PCS board “fragmented” to accommodate a spatial representation of different functions. Any orange in the graphic indicates that the part or functionality is located on the PCS board.

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This diagram is an approximation of the physical layout of the PCS board. It is intended as a working map (like the London subway map) where spatial relationships are approximate. Connectors and headers are labeled on the board and can be referenced to their labels here.

This diagram is a detail from the previous diagram. It gives the PCS microcontroller pinout, where the device is a Microchip PIC 18LF4520.

PCS 0 Best practice and precautions

Indicate power on/off rules, broken aspects of the early Gen 3.2 board…

PCS 1 Power Connectors

Must include J7 here.

PCS 2 Power Monitoring

Include JP4 and define SS6.

PCS 3 GPS Interface

Includes P3 and serial connection to COM1 on SBC

PCS 4 SBC Interface

4 bits used out of 8 in both directions, LCD = PORTC, DIO = PORTB, programming note on setting values

Gen 3.2 PCS Board Design

PCS 5 Microcontroller Programming

This has to include the RJ45 and edip switch. Note in diagram how edip 100 maps to uC pins

PCS 6 Signal Path Selection

Explicit ADC/GPIO stuff.

PCS 7 JP9 Test Header

Include note on spare voltage divider

 

For more detail: Gen 3.2 PCS Board Design




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