DRIVING DOWN THE ON RESISTANCE OF SILICON CARBIDE TRANSISTORS




UnitedSiC has developed silicon carbide transistors in standard packages with the world’s lowest on resistance. Chris Dries, CEO, talks to Nick Flaherty about the significance of the move.

UnitedSiC has launched four silicon carbide SiC transistors with the world’s lowest on resistance RDS(on) to open up new applications.

DRIVING DOWN THE ON RESISTANCE OF SILICON CARBIDE TRANSISTORS

“What we are doing is pretty incredible for the industry with an on resistance on under 10 mΩ in a standard package,” said Chris Dries, CEO of United SIC, talking to eeNews Power. “This is a real milestone for United SiC. The flagship market for us is electric vehicles, particularly in traction, but circuit protection is a new area now enabled by the low rds on,” he said.

Of the four new SiC FET devices, one is rated at 650V with RDS(on) of 7 mΩ and three rated at 1200V with RDS(on) of 9 and 16 mΩ. These are available in a TO247 package with three or four pins.

“This is an extension of the third generation platform – the maturation of the process in the fab enables us to go to these large die at high volume” said Dries. “We have created two different types of FET depending on the switching speeds – the UJ3C is general purpose that is easy as a drop in replacement, while the UF fast parts are designed for high performance hard switched.”

This comes from the design of the parts, which uses a silicon MOSFET, or cascode, alongside a JFET built in silicon carbide.

The silicon cascode MOSFET that we make is stacked on top of the JFET,” he said. “The way we are able to do it is because the underlying technology of the JFET – RDS(on) per unit area – at 1200V our specific on resistance is half at 1200V and at 650V is a quarter. That’s the key differentiator that allow us to do this where other cannot.”

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“The problem with SiC is that it does not like to form a gate oxide,” said Dries. “What we have done is use the perfect oxide of silicon as the gate interface and then we have the SiC JFET with the lowest specific rds on, so we optimise the performance of both FETs. Its really hard to do it successfully but once you can it’s the best way,” he added.

While the 4pin versions are aimed at high frequency switching, the three pin versions are drop in replacements for silicon IGBTs.

The 3pin version is to directly replace CoolMOS [devices from Infineon] in low RDS on designs. Designers can move from 2.2, 2.4kW to 3kW by replacing CoolMOS silicon with drop in SiC. Most SiC MOSFETs need a negative gate drive from -4 or -5V to +15 or 20V, but we design the gates so they are clamped at -20V so we can be pin for pin compatible with silicon IGBTs.”

Thermal management is a key part of the new devices. “What we do is silver sinter the die to the lead frame using die attach technology that allows us to get the heat out of the package. We can do a three lead (3L) package but the di/dt necessitates a four pin kelvin connected package,” he said. “In the SiC industry we all have this four lead package – Infineon, Cree, ST all have it – the switching performance is far superior and we try to steer customers to it. Those parts can run at over 100A in a TO247 package.

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