IMEC AND CADENCE TAPE OUT INDUSTRY’S FIRST 3NM PROCESSOR CHIP




Nanoelectronics research institute IMEC and Cadence Design Systems have worked together to produce a tape-out for the industry’s first 64bit processor core as a test chip to be built in a nominal 3nm node. The tape-out project, geared toward advancing 3nm chip design, was completed using extreme ultraviolet (EUV) and 193 immersion (193i) lithography-oriented design rules and Cadence tools.

IMEC AND CADENCE TAPE OUT INDUSTRY’S FIRST 3NM PROCESSOR CHIP

Cadence and Imec have created and validated GDS files using a modified Cadence tool flow. It is based on a metal stack using a 21-nm routing pitch and a 42-nm contacted poly pitch created with data from a metal layer made in an earlier experiment. The Cadence tools used include the Innovus implementation system that makes use of massively parallel computation for the physical implementation system to achieve power, performance, and area (PPA) targets. The Genus synthesis tool provides RTL synthesis that addresses FinFET process node requirements.

IMEC utilized a standard industry’s 64-bit CPU for the design with a custom 3nm standard cell library. For the project, EUV and 193i lithography rules were tested to provide the required resolution, while providing PPA comparison under two different patterning assumptions.

Imec is starting work on the masks and lithography, initially aiming to use double-patterning EUV and self-aligned quadruple patterning (SAQP) immersion processes. Over time, Imec hopes to optimize the process to use a single pass in the EUV scanner. Ultimately, fabs may migrate to a planned high-numerical-aperture version of today’s EUV systems to make 3-nm chips.

Besides the finer features, the first two layers of 3-nm chips may use different metalization techniques and metals such as cobalt, said Ryoung-Han Kim, an R&D group manager at Imec. The node is also expected to use new transistor designs such as nanowires or nanosheets rather than the FinFETs utilized in today’s 16-nm and finer processes.

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As process dimensions reduce to the 3nm node, interconnect variation becomes much more significant,” said An Steegen, executive vice president for semiconductor technology and systems at Imec. “Our work on the test chip has enabled interconnect variation to be measured and improved and the 3nm manufacturing process to be validated. Also, the Cadence digital solutions offered everything needed for this 3nm implementation. Due to Cadence’s well-integrated flow, the solutions were easy to use, which helped our engineering team stay productive when developing the 3nm rule set.

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