It is possible to reconfigure radiation-hardened Xilinx FPGAs with the reliability required for space applications, writes a team of developers from Germany-based Fraunhofer IIS RF and microwave design department
In 2017 the experimental Heinrich Hertz communications satellite (H2Sat) commissioned by the German Federal Ministry of Economics and Technology will be launched into space, to support research into communications technologies operating in the Ka and K bands.
H2Sat contains a regenerative transponder built around a reconfigurable processor developed at Fraunhofer IIS in Erlangen, Germany.
The ability to reconfigure the transponderās processor for various tasks saves space, reduces weight and enables systems to support future communications protocols.
In this example, the processor is implemented on radiation-hardened Xilinx Virtex-5QV FPGAs, which are designed to have resistance to total ionising dose and single-event effects. They also withstand high vibration and thermal cycling.
A special configuration methodology combining a new configuration method in parallel with a fail-safe partial-reconfiguration method ensures the system can be reconfigured reliably in space and is not vulnerable to a single point of failure.
The approach uses an external radiation-hardened configuration processor with a rad-hard mass memory (for example, flash). The (partial) bit file is stored in the memory and the processor configures the FPGA with the bit stream. This offers flexibility if the design requires a full FPGA reconfiguration and has many bit files on-board.
Bit files are updated or verified via a telemetry channel or a digital communication up- or downlink.
This method is non-redundant. If the processor or configuration interface fails, as illustrated in Figure 2, reconfiguration becomes impossible.
Designed to be a āfail-safe configurationā method, it allows self-reconfiguration of the FPGAs and is also used for initial configuration. Only one radiation-hardened non-volatile memory (PROM or magnetoresistive RAM) is needed per FPGA to store the initial firmware.
Using both methods in parallel combines the advantages of each while increasing reliability by overcoming the single-point-of-failure problem. Figure 2 illustrates both configuration methods for one FPGA.
About The Author
Ibrar Ayyub
I am an experienced technical writer holding a Master's degree in computer science from BZU Multan, Pakistan University. With a background spanning various industries, particularly in home automation and engineering, I have honed my skills in crafting clear and concise content. Proficient in leveraging infographics and diagrams, I strive to simplify complex concepts for readers. My strength lies in thorough research and presenting information in a structured and logical format.
Follow Us:LinkedinTwitter