FPGA makes supercomputer run faster

Altera and IBM have designed an FPGA-based reconfigurable processor to improve the performance of supercomputers.

The firms have created the first FPGA-based accelerator for a POWER8 CPU which features shared virtual memory between the FPGA and processor and so improves system performance in high-performance computing (HPC) and data centre applications for data compression, encryption, image processing and search.

Altera and IBM are presenting several POWER8 systems that are coherently accelerated using FPGAs at SuperComputing 2014.

FPGAs are connected to the POWER8 CPU using IBM’s Coherent Accelerator Processor Interface (CAPI). This makes the FPGA appear as simply another core on the POWER8 processor.

The expectation is this will shorten development time by greatly reducing lines of software code and reduced processor cycles versus conventional IO attached accelerators. A single FPGA-accelerated POWER8 server is able to operate at industry-leading levels of efficiency, allowing system architects to cut their data center footprint in half.

“With rapidly changing workloads, it is imperative we build in flexible accelerators to make IBM POWER processors more efficient in IBM Power Systems and all OpenPOWER compatible systems,” said Brad McCredie, vice president of IBM Power development and OpenPOWER president.

“The work Altera has done to provide FPGA-based reconfigurable hardware acceleration to our POWER processors enabled through CAPI allows software developers to build highly efficient, highly flexible, performance optimised systems,” said MCCredie

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